Classic Mac Hardware (Troubleshooting, Upgrading, & Modifying) > Mac OS 9 Booting on Previously Unsupported Hardware

G5 boot test reports and how we should prepare tests

(1/14) > >>

teroyk:
Yes, I know that it is little stupid dream that G5 can boot to Mac OS 9 ever, but...

...are there anybody even tested to boot the first G5 model with Mac OS 9 compatible AGP-card?
I think boot have to do from firewire-drive. Should machine have less than 2 GB memory?
Tester should have some skills to debug where boot stops. Or should first test machine be Xserve G5 cluster node and debug through RS-232?
Can Mac OS 9 boot without graphics-card?

BTW. I find information about IDE/SATA-card that is Mac OS 9 and also PCI-X (for G5) compatible:
http://www.macsense.com/product/storage/sua-100e.html

IIO:

--- Quote from: teroyk on May 31, 2020, 10:20:30 AM ---I think boot have to do from firewire-drive.

--- End quote ---

sounds the safest for now.


--- Quote ---Should machine have less than 2 GB memory?
--- End quote ---

i´d guess no. in a G4 it is fine with 2GB istalled, it just ignores the excess.


--- Quote ---Or should first test machine be Xserve G5 cluster node and debug through RS-232?
--- End quote ---

no idea if a console could tell more than other forms of debugging - or if a console will get any kind of output at all from a non posix OS.

but i think the cluster node would be the coolest machine of all for audio applications or as render server. :)


--- Quote ---Can Mac OS 9 boot without graphics-card?

--- End quote ---

yes. though i am not sure if this does not eventually depends on the hardware, too. an intel core2duo macmini for example can not boot headless without some trickery at the dvi port. (or at least you can not set a resolution)

i dont find it back, but someone who knows more already explained somewhere that the main issue is that a G5 processor simply has a completely different type of instruction set, so that you basically would have rewrite literally everything.

teroyk:

--- Quote from: IIO on May 31, 2020, 11:12:39 AM ---i dont find it back, but someone who knows more already explained somewhere that the main issue is that a G5 processor simply has a completely different type of instruction set, so that you basically would have rewrite literally everything.

--- End quote ---

Actually that cannot be true, because then any of G3/G4  Mac OSX programs cannot work in G5 (or of course in emulation they can work). There can be lot of difference and they can trapped with illegal instruction traps, but still it cannot be completely different type of instruction set.

I have to check it... ...I made fast reading "PowerPC® Microprocessor Family:The Programming Environments Manual for 32 and 64-bit Microprocessors" and I found:
"
An operating system that uses the bridge features does not take full advantage of the 64-bit implementation (for example, it can generate only 32-bit effective addresses).
An operating system that uses the 64-bit bridge architecture should observe the following:
The boot process should do the following: – ClearMSR[SF]. – Initialize the ASR, clearing ASR[V]. – Invalidate all SLB entries.
The operating system should do the following:
– Support only 32-bit applications.
– If any 64-bit instructions are used for example,to modify a PTE or a 64-bi tSPR,en sure either that exceptions cannot occur or that the exception handler saves and restores all 64 bits of the GPRs.
...
"
and some things more, that is not problem. It might be that G5 ROM-boot code start reading disks in 32-bit mode, so it might that bridge feature is default in start.

Protools5LEGuy:
For G5 to boot Mac OS 9 there also is needed an Little Endian/ Big Endian converter/wrapper written in openfirmware or Forth or Pascal I guess.

teroyk:

--- Quote from: Protools5LEGuy on May 31, 2020, 01:08:12 PM ---For G5 to boot Mac OS 9 there also is needed an Little Endian/ Big Endian converter/wrapper written in openfirmware or Forth or Pascal I guess.

--- End quote ---

Why? G5 is Big Endian too like almost all processor except Z80 and x86.

Navigation

[0] Message Index

[#] Next page

Go to full version